1. Field of the Invention
The present invention relates generally to electrical circuitry and, more particularly, to a stackable packaging system using ball grid array technology.
2. Description of the Related Art
Packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Fine-Pitch Surface Mount Technology (FPT) and Pin Grid Array (PGA) technology are well developed areas of packaging technology. An emerging packaging method has been developed using Ball Grid Array (BGA) technology.
BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multilayer interconnect options; higher I/Os for a given footprint; easier extension to multichip modules; and faster design-to-production cycle time.
While BGA technology provides many benefits, there is still a growing demand for more component functionality in a smaller space. Despite the benefits provided by BGA technology, BGA is still a surface mount technology like FPT and PGA and, thus, is limited by the space available on the mounting surface. Significant research and development has been devoted to finding ways to get more and more capabilities into smaller areas. Engineers have been challenged with finding ways to increase hardware capabilities, with memory capacity being one area in which board geography is at a particular premium is memory. However, regardless of whether FPT, PGA or BGA is implemented, surface mount technologies are limited by the space available on the ceramic substrate or printed circuit board (PCB). As a result, the amount of memory will disadvantageously be limited by the dimensions of the mounting surface.
The present invention may address one or more of the problems set forth above.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a system that includes a processor and a memory device coupled to the processor. The memory device includes a stacked ball grid array and memory chips.
In accordance with another aspect of the present invention, there is provided a stacked ball grid array. The stacked ball grid array contains a plurality of packages made up of some structural dielectric. Each package is coupled to another package and to one or more memory chips. Each package contains a die side for mounting a chip such as a memory device, and a wire side. The wire side of the package contains a plurality of solder balls used to couple one package to another. By using solder balls to connect the packages, each memory chip can be serially connected by vias contained within the packages.
In accordance with still another aspect of the present invention, the package contains alignment features on the die side and wire side. The alignment features may be male or female and are used for alignment, orientation, and ball support. A die, such as a memory chip, is mounted within the alignment features and electrically coupled to the package. Signals are routed from the memory chip to the outside of the package and connected to adjacent packages through vias and solder balls.
One advantage of the present invention is that it employs BGA technology to create a Stacked Ball Grid Array (SBGA). The memory chips are mounted to preformed packages, made for example from a molded resin, incorporating BGA technology. As previously discussed, the packages are constructed such that they contain alignment features. These features are oriented on the packages in such a way that allows the packages to be stacked. The arrangement or the features allow for alignment and orientation of each package with respect to an adjacent package, while also providing package support during the stacking and reflow process necessary to connect the packages. The alignment features provide maintenance of the stack height and parallelism between packages.
Thus, the present invention allows for increased memory capacity without requiring additional surface area on the ceramic substrate or printed circuit board to which the memory devices are electrically coupled.